1. Technical Field
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device that includes a metal-insulator-semiconductor (hereinafter, MIS) structure such as a field effect transistor.
2. Related Art
Investigations are being made on techniques for executing work function control or composition control of a gate electrode of a PMOS and NMOS transistor, in the attempt to better control the threshold voltage of the PMOS and NMOS transistor, which is essential for properly driving the transistor. Also, use of a metal electrode for preventing depletion of the gate electrode is currently focused on, and in particular the technique of forming a fully silicided (hereinafter, FUSI) gate electrode, which is a gate electrode turned into silicide down to the interface with the gate insulating layer, is being widely studied, because of the consistency with the manufacturing process so far developed.
In Japanese Laid-Open Patent Publication No. 2006-100431, it is disclosed a method of manufacturing a semiconductor device including employing polycrystalline silicon to form a gate electrode for the PMOS and the NMOS on a gate oxide nitride layer (SiON), implanting as impurity boron (B) into the gate electrode for the PMOS and arsenic (As) into the gate electrode for the NMOS respectively through a resist mask, and depositing Ni on the gate electrode for full silicidation thereof. Distributing the impurity on the interface between the gate oxide nitride layer and the FUSI gate electrode is intended for controlling the work function.
It is disclosed in IEEE 2005 “Physical Mechanism of Work Function Modulation due to Impurity Pileup at Ni-FUSI/SiO(N) Interface”, that the composition and orientation of the silicide phase depend on the impurity implanted in advance into the polysilicon before the silicidation process.
In IEDM 2004 “Dual Work function Ni-Silicide/HfSiON Gate Stacks by Phase-Controlled Full-Silicidation (PC-FUSI) Technique for 45 nm-node LSTP and LOP Devices”, and Symposium on VLSI Technology Digest of Technical Papers 2005 “Highly Reliable HfSiON CMOSFET with Phase Controlled NiSi (NFET) and Ni3Si (PFET) FUSI Gate Electrode”, phase of the FUSI gate electrodes are appropriately controlled for the PMOS transistor and the NMOS transistor by changing Ni film thickness when forming the FUSI gate electrodes on HfSiON gate insulating films. With this structure, the threshold voltage of the CMOS can be appropriately controlled.
In Symposium on VLSI Technology Digest of Technical Papers 2006 “Dual Work function Phase Controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, Reliability & Process Window Improvement by Sacrificial SiGe cap”, and IEEE 2005 “CMOS Integration of Dual Work Function Phase Controlled Ni FUSI with Simultaneous Silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) Gates on HfSiON”, the formation of FUSI electrodes having appropriate silicide phase by performing an etch back of the poly-silicon of the PMOS transistor to suppress the volume expansion at the time of forming Ni rich silicide. In these documents, impurity is not introduced into the gate electrodes and the composition of silicide phase is controlled by the thickness ratio of the Ni layer and the poly-silicon layer. In these documents, HfSiON is used as gate insulating films.
It has now been discovered by the inventor that it takes a complicated process to form the NMOS and the PMOS gate electrode from polysilicon and to properly form the silicide phase in the respective gate electrode, to thereby obtain the NMOS and the PMOS including the FUSI gate electrode. In the case of combining the composition control of the FUSI phase by impurity implantation with the etch-back process on the PMOS side, the boundary of the implantation and that of the etch-back do not coincide, which incurs insufficient stability in structure and composition in the vicinity of the boundary between the n and p gate electrodes. Such drawback is prominently observed especially when HfSiON is employed as the gate insulating layer.
The present invention has been accomplished in view of the foregoing situation, and provides a method of manufacturing a semiconductor device that facilitates obtaining a FUSI phase of a suitable composition for a NMOS transistor and a PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps.